Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system

Hirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system. SIGARCH Computer Architecture News, 38(4):8-13, 2010. [doi]

Authors

Hirokazu Morishita

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Kenta Inakagata

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Yasunori Osana

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Naoyuki Fujita

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Hideharu Amano

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