Hirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system. SIGARCH Computer Architecture News, 38(4):8-13, 2010. [doi]
@article{MorishitaIOFA10,
title = {Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system},
author = {Hirokazu Morishita and Kenta Inakagata and Yasunori Osana and Naoyuki Fujita and Hideharu Amano},
year = {2010},
doi = {10.1145/1926367.1926370},
url = {http://doi.acm.org/10.1145/1926367.1926370},
researchr = {https://researchr.org/publication/MorishitaIOFA10},
cites = {0},
citedby = {0},
journal = {SIGARCH Computer Architecture News},
volume = {38},
number = {4},
pages = {8-13},
}