Optimizing FPGA Logic Block Architectures for Arithmetic

Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz. Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. VLSI Syst., 28(6):1378-1391, 2020. [doi]

Abstract

Abstract is missing.