Gate Sizing and Buffer Insertion using Economic Models for Power Optimization - researchr publication

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Ashok K. Murugavel, N. Ranganathan. Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. In 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India. pages 195-200, IEEE Computer Society, 2004. [doi]

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