A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 /spl mu/m SOI-CMOS technology

Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara. A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 /spl mu/m SOI-CMOS technology. J. Solid-State Circuits, 35(5):751-756, 2000. [doi]

Abstract

Abstract is missing.