A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate

Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo. A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate. In IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020. pages 1, IEEE, 2020. [doi]

Abstract

Abstract is missing.