A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate

Debasish Nayak, Debiprasad Priyabrata Acharya, Prakash Kumar Rout, Umakanta Nanda. A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate. Microelectronics Journal, 73:43-51, 2018. [doi]

@article{NayakARN18,
  title = {A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate},
  author = {Debasish Nayak and Debiprasad Priyabrata Acharya and Prakash Kumar Rout and Umakanta Nanda},
  year = {2018},
  doi = {10.1016/j.mejo.2018.01.008},
  url = {https://doi.org/10.1016/j.mejo.2018.01.008},
  researchr = {https://researchr.org/publication/NayakARN18},
  cites = {0},
  citedby = {0},
  journal = {Microelectronics Journal},
  volume = {73},
  pages = {43-51},
}