Adam Neale, Manoj Sachdev. A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014. pages 1-4, IEEE, 2014. [doi]
Abstract is missing.