Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin-Ngai Sze. Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. In David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens, editors, Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011. pages 199-204, ACM, 2011. [doi]
Abstract is missing.