Mark Nodine. Preparing Rearchitected Designs for Sequential Equivalence Checking. In Ninth International Workshop on Microprocessor Test and Verification, MTV 2008, Austin, Texas, USA, 8-10 December 2008. pages 27-32, IEEE Computer Society, 2008. [doi]
@inproceedings{Nodine08,
title = {Preparing Rearchitected Designs for Sequential Equivalence Checking},
author = {Mark Nodine},
year = {2008},
doi = {10.1109/MTV.2008.8},
url = {http://dx.doi.org/10.1109/MTV.2008.8},
researchr = {https://researchr.org/publication/Nodine08},
cites = {0},
citedby = {0},
pages = {27-32},
booktitle = {Ninth International Workshop on Microprocessor Test and Verification, MTV 2008, Austin, Texas, USA, 8-10 December 2008},
publisher = {IEEE Computer Society},
isbn = {978-0-7695-3581-4},
}