Parallel-processing VLSI architecture for mixed integer linear programming

Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi, Masahiko Yoshimoto. Parallel-processing VLSI architecture for mixed integer linear programming. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. pages 2362-2365, IEEE, 2010. [doi]

Abstract

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