Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design

Yasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima. Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. In DAC. pages 253-258, 1991. [doi]

Abstract

Abstract is missing.