A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation - researchr publication authors

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Tae-young Oh, Hoeju Chung, Jun-Young Park, Ki Won Lee, Seunghoon Oh, Su-Yeon Doo, Hyoung-Joo Kim, Changyong Lee, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-Soo Ha, Young-Ryeol Choi, Young-Chul Cho, Yong-Cheol Bae, Taeseong Jang, Chulsung Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi. A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. J. Solid-State Circuits, 50(1):178-190, 2015. [doi]

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