A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery - researchr publication

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Tae-young Oh, Seung-Hyun Yi, Sung-Hyun Yang, Byong Chan Lim, Kuk-Tae Hong. A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery. In Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006. pages 745-748, IEEE, 2006. [doi]

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