Modeling Bit Multiplication Blocks for DSP Applications Using VHDL

Siddika Berna Örs, Ahmet Dervisoglu. Modeling Bit Multiplication Blocks for DSP Applications Using VHDL. In 25th EUROMICRO 99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy. pages 1402-1405, IEEE Computer Society, 1999. [doi]

Abstract

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