FPGA Hardware Acceleration of Monte Carlo Simulations for the Ising Model

Francisco Ortega-Zamorano, Marcelo A. Montemurro, Sergio Alejandro Cannas, José M. Jerez, Leonardo Franco. FPGA Hardware Acceleration of Monte Carlo Simulations for the Ising Model. IEEE Trans. Parallel Distrib. Syst., 27(9):2618-2627, 2016. [doi]

@article{Ortega-Zamorano16-0,
  title = {FPGA Hardware Acceleration of Monte Carlo Simulations for the Ising Model},
  author = {Francisco Ortega-Zamorano and Marcelo A. Montemurro and Sergio Alejandro Cannas and José M. Jerez and Leonardo Franco},
  year = {2016},
  doi = {10.1109/TPDS.2015.2505725},
  url = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2015.2505725},
  researchr = {https://researchr.org/publication/Ortega-Zamorano16-0},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. Parallel Distrib. Syst.},
  volume = {27},
  number = {9},
  pages = {2618-2627},
}