Sai Phaneendra P., Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. In 11th International Symposium on Communications and Information Technologies, ISCIT 2011, Hangzhou, China, October 12-14, 2011. pages 472-477, IEEE, 2011. [doi]
@inproceedings{PVAVMS11,
title = {Increment/decrement/2's complement/priority encoder circuit for varying operand lengths},
author = {Sai Phaneendra P. and Chetan Vudadha and Syed Ershad Ahmed and Sreehari Veeramachaneni and N. Moorthy Muthukrishnan and M. B. Srinivas},
year = {2011},
doi = {10.1109/ISCIT.2011.6092152},
url = {http://dx.doi.org/10.1109/ISCIT.2011.6092152},
researchr = {https://researchr.org/publication/PVAVMS11},
cites = {0},
citedby = {0},
pages = {472-477},
booktitle = {11th International Symposium on Communications and Information Technologies, ISCIT 2011, Hangzhou, China, October 12-14, 2011},
publisher = {IEEE},
isbn = {978-1-4577-1294-4},
}