Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang. Buffer/flip-flop block planning for power-integrity-driven floorplanning. In 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA. pages 488-493, IEEE, 2009. [doi]
Abstract is missing.