Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields

Jeng-Shyang Pan, Chiou-Yng Lee, Pramod Kumar Meher. Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields. IEEE Trans. on Circuits and Systems, 60-I(12):3195-3204, 2013. [doi]

Abstract

Abstract is missing.