Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations

Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee. Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. IEEE Transactions on Computers, 53(11):1420-1435, 2004. [doi]

Abstract

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