Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni. Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010. pages 923-926, IEEE, 2010. [doi]
@inproceedings{PedroniJP10,
title = {Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors},
author = {Volnei A. Pedroni and Ricardo P. Jasinski and Ricardo U. Pedroni},
year = {2010},
doi = {10.1109/APCCAS.2010.5775035},
url = {http://dx.doi.org/10.1109/APCCAS.2010.5775035},
researchr = {https://researchr.org/publication/PedroniJP10},
cites = {0},
citedby = {0},
pages = {923-926},
booktitle = {2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010},
publisher = {IEEE},
isbn = {978-1-4244-7454-7},
}