Advances in Automated Source-Level Debugging of Verilog Designs

Bernhard Peischl, Naveed Riaz, Franz Wotawa. Advances in Automated Source-Level Debugging of Verilog Designs. In Ngoc Thanh Nguyen, Radoslaw Katarzyniak, editors, New Challenges in Applied Intelligence Technologies. Volume 134 of Studies in Computational Intelligence, pages 363-372, Springer, 2008. [doi]

Abstract

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