Low latency check node unit architecture for nonbinary LDPC decoding

Huyen Thi Pham, Hanho Lee. Low latency check node unit architecture for nonbinary LDPC decoding. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, South Korea, October 25-28, 2016. pages 400-401, IEEE, 2016. [doi]

Abstract

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