Leandro Zafalon Pieper, Eduardo A. C. da Costa, José C. Monteiro. m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers. In 26th Symposium on Integrated Circuits and Systems Design, SBCCI 2013, Curitiba, Brazil, September 2-6, 2013. pages 1-6, IEEE, 2013. [doi]
Abstract is missing.