Jean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman. A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. on Circuits and Systems, 60-I(8):2009-2017, 2013. [doi]
@article{PlouchartFNVSRPBBYPHRTF13,
title = {A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS},
author = {Jean-Olivier Plouchart and Mark A. Ferriss and A. S. Natarajan and Alberto Valdes-Garcia and Bodhisatwa Sadhu and Alexander Rylyakov and Benjamin D. Parker and Michael P. Beakes and Aydin Babakhani and Soner Yaldiz and Larry T. Pileggi and Ramesh Harjani and Scott K. Reynolds and José A. Tierno and Daniel J. Friedman},
year = {2013},
doi = {10.1109/TCSI.2013.2265961},
url = {http://dx.doi.org/10.1109/TCSI.2013.2265961},
researchr = {https://researchr.org/publication/PlouchartFNVSRPBBYPHRTF13},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {60-I},
number = {8},
pages = {2009-2017},
}