Reducing test application time for full scan circuits by the addition of transfer sequences

Irith Pomeranz, Sudhakar M. Reddy. Reducing test application time for full scan circuits by the addition of transfer sequences. In 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan. pages 317-322, IEEE Computer Society, 2000. [doi]

Abstract

Abstract is missing.