Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija. CMOS Combinational Circuit Sizing by Stage-wise Tapering. In 1998 Design, Automation and Test in Europe (DATE 98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France. pages 985-988, IEEE Computer Society, 1998. [doi]
Abstract is missing.