A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology - researchr publication

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Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh. A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology. In 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India. pages 192, IEEE Computer Society, 1995. [doi]

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