An Architectural Support for Reduction of In-rush Current in Systems with Instruction Controlled Power Gating

Sumanta Pyne. An Architectural Support for Reduction of In-rush Current in Systems with Instruction Controlled Power Gating. In Deming Chen, Houman Homayoun, Baris Taskin, editors, Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018. pages 487-490, ACM, 2018. [doi]

Abstract

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