High-level synthesis for large bit-width multipliers on FPGAs: a case study

Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell. High-level synthesis for large bit-width multipliers on FPGAs: a case study. In Petru Eles, Axel Jantsch, Reinaldo A. Bergamaschi, editors, Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005. pages 213-218, ACM, 2005. [doi]

@inproceedings{QuanDDB05,
  title = {High-level synthesis for large bit-width multipliers on FPGAs: a case study},
  author = {Gang Quan and James P. Davis and Siddhaveerasharan Devarkal and Duncan A. Buell},
  year = {2005},
  doi = {10.1145/1084834.1084890},
  url = {http://doi.acm.org/10.1145/1084834.1084890},
  tags = {case study},
  researchr = {https://researchr.org/publication/QuanDDB05},
  cites = {0},
  citedby = {0},
  pages = {213-218},
  booktitle = {Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005},
  editor = {Petru Eles and Axel Jantsch and Reinaldo A. Bergamaschi},
  publisher = {ACM},
  isbn = {1-59593-161-9},
}