Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin. GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. In Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong, editors, Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005. pages 299-304, IEEE, 2005.
Abstract is missing.