An approach to high-level synthesis system validation using formally verified transformations

Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri. An approach to high-level synthesis system validation using formally verified transformations. In Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000. pages 80-85, IEEE Computer Society, 2000. [doi]

Abstract

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