Georgi I. Radulov, Patrick J. Quinn, Arthur H. M. van Roermund. A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz. IEEE Trans. VLSI Syst., 23(9):1941-1945, 2015. [doi]
@article{RadulovQR15a,
title = {A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz},
author = {Georgi I. Radulov and Patrick J. Quinn and Arthur H. M. van Roermund},
year = {2015},
doi = {10.1109/TVLSI.2014.2350540},
url = {http://dx.doi.org/10.1109/TVLSI.2014.2350540},
researchr = {https://researchr.org/publication/RadulovQR15a},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {23},
number = {9},
pages = {1941-1945},
}