K. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu. A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff. In 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India. pages 277-282, IEEE Computer Society, 2006. [doi]
Abstract is missing.