Nalini K. Ratha, Anil K. Jain, Diane T. Rover. FPGA-based high performance page layout segmentation. In 6th Great Lakes Symposium on VLSI (GLS-VLSI 96), March 22-23, 1996, Ames, IA, USA. pages 29-34, IEEE Computer Society, 1996. [doi]
Abstract is missing.