A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications - researchr publication authors

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Olivier Richard, Alexandre Siligaris, Franck Badets, Cedric Dehos, Cedric Dufis, Pierre Busson, Pierre Vincent, Didier Belot, Pascal Urard. A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications. In IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010. pages 252-253, IEEE, 2010. [doi]

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