A fault model for VHDL descriptions at the register transfer level

Teresa Riesgo, Javier Uceda. A fault model for VHDL descriptions at the register transfer level. In Graham Symonds, Wolfgang Nebel, editors, Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996. pages 462-467, IEEE Computer Society Press, 1996. [doi]

Abstract

Abstract is missing.