Execution modeling in self-aware FPGA-based architectures for efficient resource management

Alfonso Rodriguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo. Execution modeling in self-aware FPGA-based architectures for efficient resource management. In 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2015, Bremen, Germany, June 29 - July 1, 2015. pages 1-8, IEEE, 2015. [doi]

Abstract

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