A bipartition-codec architecture to reduce power in pipelined circuits

Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang. A bipartition-codec architecture to reduce power in pipelined circuits. In Jacob K. White, Ellen Sentovich, editors, Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999. pages 84-90, IEEE, 1999. [doi]

Abstract

Abstract is missing.