A bipartition-codec architecture to reduce power in pipelinedcircuits

Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai. A bipartition-codec architecture to reduce power in pipelinedcircuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 20(2):343-348, 2001. [doi]

Abstract

Abstract is missing.