M. Rullán, F. C. Blom, J. Oliver, C. Ferrer. Layout-level design for testability rules for a CMOS cell library. In Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993. pages 214-218, IEEE Computer Society, 1993. [doi]
Abstract is missing.