BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning

Mehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, LeRoy Winemberg, Mark Tehranipoor. BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning. In 2016 IEEE International Test Conference, ITC 2016, Fort Worth, TX, USA, November 15-17, 2016. pages 1-10, IEEE, 2016. [doi]

Abstract

Abstract is missing.