Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya. Design of High Speed Vedic Multiplier for Decimal Number System. In Hafizur Rahaman, Sanatan Chattopadhyay, Santanu Chattopadhyay, editors, Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings. Volume 7373 of Lecture Notes in Computer Science, pages 79-88, Springer, 2012. [doi]
Abstract is missing.