Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop. Formal Modeling and Verification of Controllers for a Family of DRAM Caches. IEEE Trans. on CAD of Integrated Circuits and Systems, 37(11):2485-2496, 2018. [doi]
Abstract is missing.