A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology

Martin Saint-Laurent, Animesh Datta. A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. In Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim, editors, Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. pages 159-164, ACM, 2010. [doi]

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