47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking - researchr publication related

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Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda. 47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE Trans. on Circuits and Systems, 57-I(9):2269-2278, 2010. [doi]

The following publications are possibly variants of this publication:

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stackingMitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda. cicc 2009: 449-452 [doi]

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stackingYasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda. isscc 2009: 244-245 [doi]

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory StackingMitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda. jssc, 45(1):134-141, 2010. [doi]

A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stackingMitsuko Saito, Noriyuki Miura, Tadahiro Kuroda. isscc 2010: 440-441 [doi]

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