Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano. Scalable deep neural network accelerator cores with cubic integration using through chip interface. In International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017. pages 155-156, IEEE, 2017. [doi]
Abstract is missing.