A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture - researchr publication

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Hiroki Sakurai, Shigeto Tanaka, Yasuhiro Sugimoto. A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture. IEICE Transactions, 90-A(10):2272-2279, 2007. [doi]

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