A 5-bit 1.5 GS/s ADC using reduced comparator architecture

Saloni, Manish Goswami, B. R. Singh. A 5-bit 1.5 GS/s ADC using reduced comparator architecture. In 8th International Design and Test Symposium, IDT 2013, Marrakesh, Morocco, 16-18 December, 2013. pages 1-3, IEEE, 2013. [doi]

Abstract

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