A high speed bit plane coder for JPEG 2000 and it's FPGA implementation - researchr publication

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Kishor Sarawadekar, Swapna Banerjee. A high speed bit plane coder for JPEG 2000 and it's FPGA implementation. In 17th European Signal Processing Conference, EUSIPCO 2009, Glasgow, Scotland, UK, August 24-28, 2009. pages 2231-2234, IEEE, 2009. [doi]

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